This application is related to Japanese Patent Application No. 2000-224112 filed on Jul. 25, 2000, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a transistor such as a photocoupler or the like which has a saturation-level voltage when an output transistor is ON and in which the output transistor has a reduced turn-off time (TOFF).
2. Description of Related Art
FIG. 5 shows an NPN transistor for a low saturation voltage output. In FIG. 5, the upper part and the lower part show a plan view and a sectional view, respectively, of the transistor. There are shown in the figure a substrate 1, a base 2, an emitter 3, a collector 4, an insulating film 5, a second emitter diffusion region 6, a base diffusion region 7, an epitaxial region 8, a collector compensation diffusion region 9, an buried diffusion region 10, an isolation diffusion region 11 and a first emitter diffusion region 12.
In designing the transistor, the specific resistance and thickness of the epitaxial region is so determined to endure the maximum voltage applied, and the area of the emitter is so determined to allow the maximum output current to flow. The collector compensation diffusion region is so arranged to encircle the base and the emitter for reducing a collector resistance and decreasing the saturation voltage with the determined area of the emitter.
Transistors such as a photocoupler may mal-operate in an environment where noise is large. For this reason, a grounded-emitter current gain (hFE) in a reverse direction needs to be raised. That is, the transistor is so designed that its base and emitter are enclosed by the collector compensation region and the buried diffusion region.
FIG. 7 illustrates a switching waveform when a pulse is input to the base of a prior art transistor. A current is supplied to the base so that an output Vc is saturated and is a sufficiently low voltage when the transistor is ON. However, when the saturation becomes deep, the transistor turns OFF and a turn-off time (tOFF) is prolonged which is necessary for the potential of the collector to change from low to high.
The tOFF is the sum of a falling time (tf) in which Vc changes from 10% to 90% and a storage time (ts) from the moment when the input pulse to the base is cut until the moment when Vc becomes 10%.
When the saturation becomes deep, ts of tOFF becomes large. This results from the remaining of carriers stored in an ON state. In the On state, the transistor operates in a saturation region, and a collector junction is in a forward bias state and carriers are injected thereto. Thereby, in the epitaxial region enclosed by the base region, the collector, the buried diffusion region (N+) and the collector compensation diffusion region (N+), an excess minority carrier deposit more than in an active state. After the input pulse is ceased and the polarity of voltage input to the base is reversed, the excess minority carrier remains during the Ts period. The excess minority carrier recombines or is removed from the base by an inverse base current Ibr, and the collector junction becomes into an inverse bias state. Then the current to the collector begins to decrease. When the minority carrier decreases further and the excess carrier disappears, the transistor is turned off.
The storage time ts is represented by the following formula:
ts=xcfx84pln(xcex2FIB/IC), 
wherein
xcfx84p: the life of the minority carrier in the base region,
xcex2F: grounded-emitter current-amplification factor.
Here, in the case where xcex2F is intended to be decreased for reducing ts, xcex2F is determined by the maximum current output by the transistor in combination with the emitter area. In the case where xcfx84p is intended to be reduced, the amount of the minority carrier injected in the epitaxial region may be reduced. For this purpose, the area of the epitaxial region may be reduced or the thickness thereof may be reduced. However, the area of the epitaxial region is almost determined by the above-mentioned area of the emitter. The specific resistance and the thickness of the epitaxial region are so determined to endure the maximum voltage applied to the transistor.
In order to solve the above-described problems, the inventor of the present invention has directed his attention to the reduction of xcfx84p. That is, xcfx84p is reduced by drawing out the minority carrier injected excessively in the base and the epitaxial region. More particularly, a parasitic PNP transistor is provided in the transistor, and at the deep saturation, the parasitic PNP transistor operates to draw the minority carrier from the base to reduce ts. Consequently, xcfx84p can be decreased.
Thus, according to the present invention, there is provided a transistor comprising an NPN transistor provided with an N-type emitter, a P-type base, an N-type collector, an emitter diffusion region and a collector compensation diffusion region around the base and the emitter for decreasing a saturation voltage; and a parasitic PNP transistor in a region where the NPN transistor is formed, the parasitic PNP transistor operating under saturation of the NPN transistor.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.